From b81328a44212bb318e196b5d4b02f861f101fee3 Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 3 Feb 2025 13:13:54 -0700 Subject: [PATCH] vault backup: 2025-02-03 13:13:54 --- .../computer engineering/ECE2700/Homework/Homework 2.md | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/education/computer engineering/ECE2700/Homework/Homework 2.md b/education/computer engineering/ECE2700/Homework/Homework 2.md index ac94d46..49497dc 100644 --- a/education/computer engineering/ECE2700/Homework/Homework 2.md +++ b/education/computer engineering/ECE2700/Homework/Homework 2.md @@ -1,6 +1,10 @@ -# Feb 3, 2025 ECE2700; HW 2 Boehme, James +# Feb 3, 2025 | ECE2700; HW 2 | Boehme, James +--- # 1. -## Problem Statement: +## Problem Statement: +> Describe in Verilog, a full adder that accepts the following three one bit inputs: $x$, $y$, and the carry-in bit $c$; and it generates the following two one-bit outputs: the sum bit $sum$ and the carry-out bit $cout$. + +> Part a) For the first full-adder design, describe the $sum$ output using ## Given ## Find