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education/computer engineering/ECE2700/Adders.md
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# Half Adder
#
# Ripple Carry Adder
# Carry-Select Adder # Carry-Select Adder
A carry select adder is built using two ripple carry adders, and multiplexing them together based off of the value of $c_{in}$. This is done for performance reasons, because when adding two numbers $x$ and $y$, we know $x$ and $y$ *before* we know the value of $c_{in}$. This means we can compute what the output of $x + y + c_{in}$ would be for $c_{in} = 0$ and $c_{in} = 1$ at the same time, then just toggle between the two possible values given the *actual* value of $c_{in}$. A carry select adder is built using two ripple carry adders, and multiplexing them together based off of the value of $c_{in}$. This is done for performance reasons, because when adding two numbers $x$ and $y$, we know $x$ and $y$ *before* we know the value of $c_{in}$. This means we can compute what the output of $x + y + c_{in}$ would be for $c_{in} = 0$ and $c_{in} = 1$ at the same time, then just toggle between the two possible values given the *actual* value of $c_{in}$.

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education/computer engineering/ECE2700/Verilog/Types.md
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``` ```
# Variables # Variables
A variable is a data storage element. They retain the last impu A variable is a data storage element. They retain the last input given.
## Registers
A `reg` can be used to model hardware registers because it stores a value until the next assignment.
### Integer
A Verilog `integer` type is a 32 bit wide storage value. It does not *need* to store integers, it can be used for other purposes.
```verilog
integer count;
```
### Time
A `time` variable is unsigned, 64 bits wide, and can be used to store time duration for debugging purposes. `realtime` is similar, but time is stored as a floating bit value.
# Scalar and Vector Types # Scalar and Vector Types