vault backup: 2025-02-03 10:19:24

education/computer engineering/ECE2700/Verilog/Types.md

@@ -19,5 +19,16 @@ module foo;
 ```
 
 # Variables
-A variable is a data storage element. They retain the last impu
+A variable is a data storage element. They retain the last input given.
+
+## Registers
+A `reg` can be used to model hardware registers because it stores a value until the next assignment.
+
+### Integer
+A Verilog `integer` type is a 32 bit wide storage value. It does not *need* to store integers, it can be used for other purposes.
+```verilog
+	integer   count;
+```
+### Time
+A `time` variable is unsigned, 64 bits wide, and can be used to store time duration for debugging purposes. `realtime` is similar, but time is stored as a floating bit value.
 # Scalar and Vector Types