From 64764837b3abf4c0c34ca0298fc477b0da99118f Mon Sep 17 00:00:00 2001 From: arc Date: Fri, 17 Jan 2025 15:03:02 -0700 Subject: [PATCH] vault backup: 2025-01-17 15:03:02 --- education/computer engineering/ECE2700/Verilog.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md index a84a83a..15fa03c 100644 --- a/education/computer engineering/ECE2700/Verilog.md +++ b/education/computer engineering/ECE2700/Verilog.md @@ -13,3 +13,13 @@ - Usable in combination with schematic design # Verilog +- Originally developed by Gateway Design Automation +- Put in public domain in 1990 +- Standardized in 1995 +- Originally intended for simulation of logic networks, later adapted to synthesis + +```verilog +module example1(x1, x2, s, f); + input x1, x2, s; + +``` \ No newline at end of file