diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md
index a84a83a..15fa03c 100644
--- a/education/computer engineering/ECE2700/Verilog.md	
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@@ -13,3 +13,13 @@
 	- Usable in combination with schematic design
 
 # Verilog
+- Originally developed by Gateway Design Automation
+- Put in public domain in 1990
+- Standardized in 1995
+- Originally intended for simulation of logic networks, later adapted to synthesis
+
+```verilog
+module example1(x1, x2, s, f);
+	input x1, x2, s;
+	
+```
\ No newline at end of file