From 5898de24cb5428c132c51a7e165252c318f10a68 Mon Sep 17 00:00:00 2001 From: arc Date: Wed, 29 Jan 2025 10:37:26 -0700 Subject: [PATCH] vault backup: 2025-01-29 10:37:25 --- education/computer engineering/ECE2700/Adders.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/education/computer engineering/ECE2700/Adders.md b/education/computer engineering/ECE2700/Adders.md index 7a1fc48..f221fbe 100644 --- a/education/computer engineering/ECE2700/Adders.md +++ b/education/computer engineering/ECE2700/Adders.md @@ -4,4 +4,4 @@ A carry select adder is built using two ripple carry adders, and multiplexing th The delay is calculated like so: 1. Given the delay of a full adder is $k$, and the delay of a 2 to 1 mux is $\frac{1}{m}k$, 2. then the delay of a 4 bit ripple carry adder is $4k$, because it's 4 full adders chained together, running sequentially. -3. This means that the delay of a 4 bit \ No newline at end of file +3. This means that the delay of a 4 bit carry select adder is $4k + \frac{k}{m}$ \ No newline at end of file