diff --git a/education/computer engineering/ECE2700/Adders.md b/education/computer engineering/ECE2700/Adders.md
index 7a1fc48..f221fbe 100644
--- a/education/computer engineering/ECE2700/Adders.md	
+++ b/education/computer engineering/ECE2700/Adders.md	
@@ -4,4 +4,4 @@ A carry select adder is built using two ripple carry adders, and multiplexing th
 The delay is calculated like so:
 1. Given the delay of a full adder is $k$, and the delay of a 2 to 1 mux is $\frac{1}{m}k$,
 2. then the delay of a 4 bit ripple carry adder is $4k$, because it's 4 full adders chained together, running sequentially.
-3. This means that the delay of a 4 bit 
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+3. This means that the delay of a 4 bit carry select adder is $4k + \frac{k}{m}$ 
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