From 400c362f17fa233ab7edccf84a7f5401f5085fe9 Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 3 Feb 2025 10:04:19 -0700 Subject: [PATCH] vault backup: 2025-02-03 10:04:19 --- education/computer engineering/ECE2700/Verilog/Modules.md | 4 +++- education/computer engineering/ECE2700/Verilog/Types.md | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) create mode 100644 education/computer engineering/ECE2700/Verilog/Types.md diff --git a/education/computer engineering/ECE2700/Verilog/Modules.md b/education/computer engineering/ECE2700/Verilog/Modules.md index 66d89d6..7bef14f 100644 --- a/education/computer engineering/ECE2700/Verilog/Modules.md +++ b/education/computer engineering/ECE2700/Verilog/Modules.md @@ -38,4 +38,6 @@ There are 3 kinds of ports: - `inout`: Inout ports can send *and* receive values. ### Port types -If no \ No newline at end of file +If no type is defined, ports are implicitly defined as *nets* of type `wire`. + +> In verilog, the term *net* refers to network, and it refers to a connection that joins two or more devices together. diff --git a/education/computer engineering/ECE2700/Verilog/Types.md b/education/computer engineering/ECE2700/Verilog/Types.md new file mode 100644 index 0000000..2244096 --- /dev/null +++ b/education/computer engineering/ECE2700/Verilog/Types.md @@ -0,0 +1,2 @@ +There are two main categories of data types in Verilog. These ty +# Nets