From 32186127e2c1f76deeb817126ef4ef26380ff186 Mon Sep 17 00:00:00 2001
From: arc <zleyyij@users.noreply.github.com>
Date: Mon, 3 Feb 2025 11:19:08 -0700
Subject: [PATCH] vault backup: 2025-02-03 11:19:08

---
 .../ECE2700/Verilog/Modules.md                | 24 ++++++++++++++++++-
 .../ECE2700/Verilog/Types.md                  |  8 +++++++
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/education/computer engineering/ECE2700/Verilog/Modules.md b/education/computer engineering/ECE2700/Verilog/Modules.md
index 7bef14f..4c9c79d 100644
--- a/education/computer engineering/ECE2700/Verilog/Modules.md	
+++ b/education/computer engineering/ECE2700/Verilog/Modules.md	
@@ -21,7 +21,7 @@ Below is an example of the structure of a half adder module:
 ```verilog
 module half_adder(
 	input a,
-	input b
+	input b,
 	output sum_bit,
 	output carry_bit
 	);
@@ -37,7 +37,29 @@ There are 3 kinds of ports:
 - `output`: Output ports can be written to, but not read from.
 - `inout`: Inout ports can send *and* receive values.
 
+Ports can be declared in the port list, or in the module body. Ports declared in the port list can optionally omit their type, to be specified within the body of the module:
+```verilog
+module half_adder(
+	a,
+	b,
+	sum_bit,
+	carry_bit
+	);
+	input a;
+	input b;
+	output sum_bit;
+	output carry_bit;
+endmodule
+```
+
 ### Port types
 If no type is defined, ports are implicitly defined as *nets* of type `wire`.
 
 > In verilog, the term *net* refers to network, and it refers to a connection that joins two or more devices together.
+
+Ports can be a vector type:
+```verilog
+module test(a, b, c);
+		
+endmodule
+```
\ No newline at end of file
diff --git a/education/computer engineering/ECE2700/Verilog/Types.md b/education/computer engineering/ECE2700/Verilog/Types.md
index 2fb26fe..e77098f 100644
--- a/education/computer engineering/ECE2700/Verilog/Types.md	
+++ b/education/computer engineering/ECE2700/Verilog/Types.md	
@@ -77,4 +77,12 @@ reg [7:0] foo;
 
 // Write to bit 0
 foo [0] = 1;
+```
+
+## Part selects
+A range of contiguous bits from within another vector can be selected, referred to as a part select. This range can then be treated as a vector.
+```verilog
+reg [31:0] foo;
+// Select bits 23 through 16 (inclusive), and assign the 8 bit hex value `0xff` to them.
+foo [23:16] = 8'hff;
 ```
\ No newline at end of file