From 116ab612fcb4e3ef077542474c509d705c19942a Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 3 Feb 2025 11:14:08 -0700 Subject: [PATCH] vault backup: 2025-02-03 11:14:08 --- .../ECE2700/Verilog/Types.md | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/education/computer engineering/ECE2700/Verilog/Types.md b/education/computer engineering/ECE2700/Verilog/Types.md index 05d65f3..2fb26fe 100644 --- a/education/computer engineering/ECE2700/Verilog/Types.md +++ b/education/computer engineering/ECE2700/Verilog/Types.md @@ -56,5 +56,25 @@ A `time` variable is unsigned, 64 bits wide, and can be used to store time durat ## Real The `real` type denotes a floating point value. +## Strings +Strings are stored in a vector of `reg`s. The width of the `reg` *must* be large enough to hold the string. +Each character in a string represents a one byte ASCII value. If the size of the variable is smaller than the string, the string is truncated. # Scalar and Vector Types +By default, declarations of a net or `reg` value is 1 bit wide, referred to as a *scalar* value (only a single value). + +```verilog +// Scalar declaration +wire foo; +// Vector declaration, with 8 bits. +wire [7:0] bar; +``` + +Individual bits in a vector can be accessed using array operators, eg `[i]`. + +```verilog +reg [7:0] foo; + +// Write to bit 0 +foo [0] = 1; +``` \ No newline at end of file