From 0acfe2ddd345df81e0532c32428191ec71d2d186 Mon Sep 17 00:00:00 2001 From: arc Date: Mon, 27 Jan 2025 10:42:59 -0700 Subject: [PATCH] vault backup: 2025-01-27 10:42:59 --- education/computer engineering/ECE2700/Verilog.md | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md index 5eb115f..4320573 100644 --- a/education/computer engineering/ECE2700/Verilog.md +++ b/education/computer engineering/ECE2700/Verilog.md @@ -52,6 +52,11 @@ endmodule - Structural Verilog describes how things are laid out at a logic level ## Testbench Layout - +- Define UUT module +- Initialize Inputs +- Wait +- Test every possible combination of inputs and validate that the outputs are correct + +- $\$display("Hello, world)$