diff --git a/education/computer engineering/ECE2700/Verilog.md b/education/computer engineering/ECE2700/Verilog.md
index 5eb115f..4320573 100644
--- a/education/computer engineering/ECE2700/Verilog.md	
+++ b/education/computer engineering/ECE2700/Verilog.md	
@@ -52,6 +52,11 @@ endmodule
 - Structural Verilog describes how things are laid out at a logic level
 
 ## Testbench Layout
-
+- Define UUT module
+- Initialize Inputs
+- Wait
+- Test every possible combination of inputs and validate that the outputs are correct
+
+- $\$display("Hello, world)$