diff --git a/education/computer engineering/ECE2700/Homework/Homework 2.md b/education/computer engineering/ECE2700/Homework/Homework 2.md
index bf0a7cd..69361f1 100644
--- a/education/computer engineering/ECE2700/Homework/Homework 2.md	
+++ b/education/computer engineering/ECE2700/Homework/Homework 2.md	
@@ -18,7 +18,16 @@ $$ cout = xy + xc_i + yc_i $$
 
 ---
 # <u>Solution:</u>
-## A
+## a)
+
+---
+
+## b)
+
+---
+## c)
+
+
 ---
 ---
 # 2.
@@ -27,4 +36,6 @@ $$ cout = xy + xc_i + yc_i $$
 ## Given
 ## Find
 ---
+# <u>Solution</u>
+---
 ---
diff --git a/education/computer engineering/ECE2700/Verilog/Verilog.md b/education/computer engineering/ECE2700/Verilog/Verilog.md
index 4aed32a..a14ea62 100644
--- a/education/computer engineering/ECE2700/Verilog/Verilog.md	
+++ b/education/computer engineering/ECE2700/Verilog/Verilog.md	
@@ -32,24 +32,24 @@ module example1(x1, x2, s, f);
 	and(g, k, x1);
 	and(h, s, x2);
 	or(f, g, h);
+	// You can also do this
+	assign f = (~s & x1) | (s & x2);
 endmodule	
 ```
 
+- Structural Verilog describes how things are laid out at a logic level.
+- 
 ```verilog
 //              V---V---v--v-----portlist (not ordered)
 module example1(x1, x2, s, f);
 	// Defining the types of the various ports
 	input x1, x2, s;
 	output f;
-	// You can also do this
-	assign f = (~s & x1) | (s & x2);
-	// Or this
 	always @(a, b)
 	// always @(....) says "do this stuff whenever any of the values inside of @(...) change"
 		{s1, s0} = a + b;
 endmodule	
 ```
-- Structural Verilog describes how things are laid out at a logic level
 
 ## Testbench Layout
 - Define UUT module