There are two main categories of data types in Verilog. These categories differ in the underlying hardware structure they represent, and they differ in the way they are assigned and retain values.
# Nets
A *net* refers to a *network* of connections that join two or more devices together.

Nets connect different hardware entities and *do not store values*. 
## Wire
A `wire` is the most commonly used type of net. When a port is declared in Verilog, it is implicitly given a type of `wire`.

It is illegal to re-declare a name already in use by a net:
```verilog
module foo;
	wire abc;
	wire a;
	wire b;
	wire c;

	wire abc; // ILLEGAL: The wire `abc` is already defined

```

# Variables
A variable is a data storage element. They retain the last input given.
```verilog
```verilog
module testbench;
  integer  	int_a; 				// Integer variable
  real 		real_b; 			// Real variable
  time 		time_c; 			// Time variable

  initial begin
    int_a 	= 32'hfacd_1b34; 	// Assign an integer value
    real_b 	= 0.1234567; 		// Assign a floating point value

    #20; 						// Advance simulation time by 20 units
    time_c 	= $time; 			// Assign current simulation time

    // Now print all variables using $display system task
    $display ("int_a 	= 0x%0h", int_a);
    $display ("real_b 	= %0.5f", real_b);
    $display ("time_c 	= %0t", time_c);
  end
endmodule
```
```
## Registers
A `reg` can be used to model hardware registers because it stores a value until the next assignment.

### Integer
A Verilog `integer` type is a 32 bit wide storage value. It does not *need* to store integers, it can be used for other purposes.
```verilog
	integer   count;
```
### Time
A `time` variable is unsigned, 64 bits wide, and can be used to store time duration for debugging purposes. `realtime` is similar, but time is stored as a floating bit value.

## Real
The `real` type denotes a floating point value.

## Strings
Strings are stored in a vector of `reg`s. The width of the `reg` *must* be large enough to hold the string.

Each character in a string represents a one byte ASCII value. If the size of the variable is smaller than the string, the string is truncated.
# Scalar and Vector Types
By default, declarations of a net or `reg` value is 1 bit wide, referred to as a *scalar* value (only a single value).

```verilog
// Scalar declaration
wire foo;
// Vector declaration, with 8 bits.
wire [7:0] bar;
```

Individual bits in a vector can be accessed using array operators, eg `[i]`.

```verilog
reg [7:0] foo;

// Write to bit 0
foo [0] = 1;
```

## Part selects
A range of contiguous bits from within another vector can be selected, referred to as a part select. This range can then be treated as a vector.
```verilog
reg [31:0] foo;
// Select bits 23 through 16 (inclusive), and assign the 8 bit hex value `0xff` to them.
foo [23:16] = 8'hff;
```